This invention relates generally to the manufacture of high speed semiconductor microprocessors, application specific integrated circuits (ASICs), and other high speed integrated circuit devices. More particularly, this invention relates to the art of creating layered ultra-thin amorphous structures. Specifically, this invention relates to a novel method of forming a uniform layered structure comprising an ultra-thin layer of amorphous silicon and its thermal oxide. Useful embodiments include a method of fabricating hard mask and a method of fabricating thin polycrystalline layer of silicon-on-insulator.
Ultra thin layers of semiconductors are employed in a variety of electronic devices. For instance, various quantum well and superlattice structures have found applications in High Electron Mobility Transistors (HEMTs), laser diodes, light emitting diodes, and photodetectors. Such structures include ultra thin layers (less than 200 xc3x85) of a crystalline semiconductor. The structures are fabricated with the well known lattice matching and epitaxial techniques.
Metal-Insulator-Semiconductor (MIS) structures are used in most logic, memory, and display circuits due to the low power consumption of MISFETs and the existence of mature process technology. The performance of MISFETs can be improved if they are formed on a Semiconductor-on-Isolator (SOI) substrate. If the semiconductor layer of the SOI substrate is thinned to below 100 xc3x85, the performance of the short-channel MISFETs can be improved even further. Clearly, the insulator-semiconductor-insulator structure with an ultra thin layer of semiconductor is highly desirable.
Amorphous and polycrystalline semiconductors are employed in Thin Film Transistors (TFTs). At the moment, TFTs are used in various display panels. TFTs also may be employed in three dimensional (3D) integrated circuits where the active devices are stacked on top of each other.
One possible way to increase performance of TFT is similar to that of the crystalline MISFET: thinning down its channel to below 100 xc3x85. However, no process is known that can produce a uniform ultra thin layer of amorphous or polycrystalline semiconductor on insulator. Due to a different lattice structure, the deposition of a polycrystalline film onto an amorphous film proceeds through an island growth at the beginning of the process. For instance, in order to form a continuous film of polycrystalline silicon, one must deposit at least 150-200 xc3x85. Deposition of an amorphous silicon film may improve the situation somewhat but still limits the thickness of a uniform thin film to above 100-150 xc3x85.
Thus, there is a need in the art for a method of forming uniform ultra thin layers of amorphous and polycrystalline silicon and related layered structures.
Since its invention in 1960 the thermal oxidation of silicon is considered to be the enabling process for modern integrated circuits. After over more than four decades of extensive investigation there is a vast art on various aspects of the thermal oxidation and its applications to the fabrication of integrated circuits and other microstructures. There are several key properties of thermal oxidation that distinguish it from other methods of forming dielectric on semiconductor. These properties are: (1) a nearly electrically perfect interface between silicon and silicon oxide, (2) high dielectric strength of the oxide, and (3) excellent control of the uniformity of the oxide film. Due to these properties the thermal oxide has been used as the gate dielectric, the isolator in various LOCOS (local isolation of silicon) structures, the isolator for various IT (isolation trench) structures, the gate sidewall isolator/spacer, the screen oxide for ion implantation, etc.
Thermal oxidation of amorphous and polycrystalline silicon-containing materials also has been extensively used in IC manufacturing. Such applications include the poly buffered LOCOS, the gate sidewall isolator/spacer, the gate insulator for TFT, and other applications.
The low temperature oxidation of amorphous and polycrystalline silicon-containing materials is also known in the art. The following patents are related to low temperature oxidation.
U.S. Pat. No. 5,412,246 to Dobuzinsky et al. describes a plasma assisted oxidation of silicon and silicon nitride performed at a low plasma power. Dobuzinsky et al. teach that a high power plasma oxidation may cause damage to the grown oxide film. Therefore, a low plasma power process was selected to produce high-quality oxide films. Dobuzinsky et al. also disclose useful embodiments such as a low-temperature method of forming an oxide spacer on a doped gate. However, Dobuzinsky et al. do not teach any method of forming a nanolaminate with ultra-thin layer of amorphous or polycrystalline silicon-containing semiconductor.
U.S. Pat. No. 5,443,863 to Neely et al. describes a low temperature plasma assisted oxidation process. The plasma is created up stream of the processing zone with a microwave plasma electrical discharge. Neely et al. teach that such oxidation process can be conducted at a temperature below 300xc2x0 C. Neely et al. describe a useful embodiment where a silicon carbide film is oxidized at a low temperature. However, Neely et al. do not teach any method of forming a nanolaminate with ultra-thin layer of amorphous or polycrystalline silicon-containing semiconductor.
U.S. Pat. No. 5,738,909 to Thakur et al. describes a method of forming thin oxides on a semiconductor substrate. Thakur et al. teach a method where a portion of the oxidation process is conducted in an ozone ambient in order to increase the oxide growth rate. In addition, Thakur et al. teach that an ultraviolet radiation can speed up the oxidation process even further. However, Thakur et al. do not teach any method of forming a nanolaminate with ultra-thin layer of amorphous or polycrystalline silicon-containing semiconductor.
U.S. Pat. No. 5,700,699 to Han et al. describes a method of forming gate oxide for thin film transistor (TFT). The gate oxide is formed with plasma assisted oxidation. The plasma is created with the aid of electron cyclotron resonance (ECE) electrical discharge. The preferred range of the deposited polysilicon layer is from 2,000 to 4,000 xc3x85. Clearly, this range is far from the ultra thin regime. Consequently, Han et al. do not teach any method of forming a nanolaminate with ultra-thin layer of amorphous or polycrystalline silicon-containing semiconductor.
U.S. Pat. No. 5,238,849 to Sato describes a method of fabricating bipolar transistor. Sato teaches a method of forming an oxide layer between the crystalline base and polycrystalline emitter. The layer is formed with oxygen ions resulting in a substoichiometric silicon oxide. Sato neither teaches about the oxidation of the polycrystalline film nor provides any method of forming a nanolaminate with ultra-thin layer of amorphous or polycrystalline silicon-containing semiconductor.
Clearly, there remains a need in the art for a method of forming uniform ultra thin layers of amorphous and polycrystalline silicon and related layered structures. The present invention disclosure is directed toward a method for fabricating such nanolaminates.
One objective of this invention is to provide a method of creating a nanolaminate with thin and uniform layer of amorphous or polycrysaline silicon.
Another objective of this invention is to provide a method of forming a hard mask containing a nanolaminate with thin and uniform layer of amorphous or polycrystalline silicon.
These and other objects of this invention are accomplished by use of the methods of the present invention. In one aspect, a method for forming a nanolaminate of a silicon-containing material and an oxide on a substrate is disclosed herein. The method comprises the steps of: depositing a film containing an amorphous silicon-containing material onto the substrate, the film having an initial thickness; oxidizing the amorphous silicon-containing film by exposing the substrate to a gaseous mixture comprising atomic oxygen and molecular oxygen, wherein the ratio of atomic oxygen to molecular oxygen is about 0.00001 to 100, thereby forming a layer of oxide on the film, wherein after oxidation the film has a final thickness less than the initial thickness; and removing the oxide using, for example, a selective wet chemistry stripping process.
In another aspect, a method for forming a patterned hard mask on a substrate is disclosed, the patterned hard mask including a nanolaminate of a silicon-containing material and an oxide. The method comprises the steps of: depositing a film containing an amorphous silicon-containing material onto the substrate, the film having an initial thickness; oxidizing the amorphous silicon-containing film by exposing the substrate to a gaseous mixture comprising atomic oxygen and molecular oxygen, wherein the ratio of atomic oxygen to molecular oxygen is about 0.00001 to 100, thereby forming a layer of oxide on the film, wherein after oxidation the film has a final thickness less than the initial thickness; and patterning the layer of oxide using a lithography process, thereby exposing preselected areas of the amorphous silicon-containing film.
In yet another aspect of the present invention, a semiconductor structure is disclosed. The structure comprises a substrate; and a silicon-containing film on the substrate, the silicon-containing film having a thickness of less than about 100 xc3x85, preferably less than about 80 xc3x85, more preferably about 50 xc3x85, and preferably with a uniformity of better than about 3 xc3x85 at 1 sigma standard deviation. The silicon-containing film may be either amorphous or polycrystalline. The semiconductor structure may further comprise a patterned thermal oxide film on the silicon-containing film, the patterned thermal oxide film having a thickness of at least about 50 xc3x85. The structure may further comprise an insulating layer on the silicon-containing film; and an electrode layer on the insulating layer, the electrode having an electrical bias with respect to the silicon-containing film such that an electrical field is created across the insulating layer.